`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/20 09:56:19
// Design Name: 
// Module Name: clk_50m_1m
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clk_50m_1m(
    input       rst_n,
    input       clk_in_50m,
    output reg  clk_out_1m
    );
localparam DEVIDE_N = 10;
wire                    clk_10m;
wire                    locked;
reg [DEVIDE_N/2-1:0]    clk_cnt;

always @(posedge clk_10m or negedge rst_n) begin
    if (!rst_n) begin
        clk_cnt <= 0;
        clk_out_1m  <= 0;
    end else if (clk_cnt == DEVIDE_N/2-1) begin
        clk_cnt <= 0;
        clk_out_1m  <= ~clk_out_1m;
    end else begin
        clk_cnt <= clk_cnt + 1;
    end
end


pll_clk u_pll_clk//TODO
(
    // Clock out ports
    .clk_out1(clk_10m),     // output clk_out1
    // Status and control signals
    .reset(~rst_n), // input reset
    .locked(locked),       // output locked
    // Clock in ports
    .clk_in1(clk_in_50m)      // input clk_in1
    );
endmodule
